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TMS626162A 524288 by 16-bit by 2-bank synchronous dynamic random-access memory smos692b july 1997 revised march 1998 1 post office box 1443 ? houston, texas 772511443 synchronous clock cyle time access time clock to output refresh interval t ck3 (cl 2 = 3) t ck2 (cl = 2) t ac3 (cl = 3) t ac2 (cl = 2) t ref '626162a-10 10 ns 15 ns 7 ns 7 ns 64 ms 2 cl = cas latency description the TMS626162A is a high-speed 16 777 216-bit synchronous dynamic random-access memory (sdram) device organized as two banks of 524 288 words with 16 bits per word. please be aware that an important notice concerning availability, standard warranty, and use in critical applications of texas instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. pin nomenclature a[0: 10] address inputs a0 a10 row addresses a0 a7 column addresses a10 automatic-precharge select a11 bank select cas column-address strobe cke clock enable clk system clock cs chip select dq[0 : 15] sdram data input / output dqml, dqmu data input / output mask enable nc no connect ras row-address strobe v cc power supply (3.3-v typical) v ccq power supply for output drivers (3.3-v typical) v ss ground v ssq ground for output drivers w write enable 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 v ss dq15 dq14 v ssq dq13 dq12 v ccq dq11 dq10 v ssq dq9 dq8 v ccq nc dqmu clk cke nc a9 a8 a7 a6 a5 a4 v ss 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 v cc dq0 dq1 v ssq dq2 dq3 v ccq dq4 dq5 v ssq dq6 dq7 v ccq dqml w cas ras cs a11 a10 a0 a1 a2 a3 v cc dge package ( top view ) organization 512k 16 bits 2 banks 3.3-v power supply ( 10% tolerance) two banks for on-chip interleaving (gapless accesses) high bandwidth up to 100-mhz data rates cas latency (cl) programmable to two or three cycles from column-address entry burst sequence programmable to serial or interleave burst length programmable to 1, 2, 4, 8, or full page chip select and clock enable for enhanced-system interfacing cycle-by-cycle dq-bus mask capability with upper- and lower-byte control auto-refresh and self-refresh capability 4k refresh (total for both banks) high-speed, low-noise, low-voltage ttl (lvttl) interface power-down mode compatible with jedec standards pipeline architecture temperature ranges: operating, 0 c to 70 c storage, 55 c to 150 c copyright ? 1998, texas instruments incorporated production data information is current as of publication date. products conform to specifications per the terms of texas instruments standard warranty. production processing does not necessarily include testing of all parameters.
TMS626162A 524288 by 16-bit by 2-bank synchronous dynamic random-access memory smos692b july 1997 revised march 1998 2 post office box 1443 ? houston, texas 772511443 description (continued) all inputs and outputs of the TMS626162A series are compatible with the lvttl interface. the sdram employs state-of-the-art technology for high performance, reliability, and low power. all inputs and outputs are synchronized with the clk input to simplify system design and enhance use with high-speed microprocessors and caches. the TMS626162A sdram is available in a 400-mil, 50-pin surface-mount tsop package (dge suffix). functional block diagram clk cke cs dqmx ras cas w a0 a11 control mode register array bank t array bank b dq buffer dq0 dq15 16 12 operation all inputs to the '626162a sdram are latched on the rising edge of the system (synchronous) clock. the outputs, dq0 dq15, are also referenced to the rising edge of clk. the '626162a has two banks that are accessed independently. a bank must be activated before it can be accessed (read from or written to). refresh cycles refresh both banks alternately. six basic commands or functions control most operations of the '626162a: bank activate/row-address entry column-address entry/write operation column-address entry/read operation bank deactivate auto-refresh self-refresh additionally, operations can be controlled by three methods: using chip select (cs ) to select / deselect the devices, using data/output mask enables (dqmx) to enable/mask the dq signals on a cycle-by-cycle basis, or using clock enable (cke) to suspend the system clock (clk) input. the device contains a mode register that must be programmed for proper operation. table 1 through table 3 show the various operations that are available on the '626162a. these truth tables identify the command and/or operations and their respective mnemonics. each truth table is followed by a legend that explains the abbreviated symbols. an access operation refers to any read or write command in progress at cycle n. access operations include the cycle upon which the read or write command is entered and all subsequent cycles through the completion of the access burst.
TMS626162A 524288 by 16-bit by 2-bank synchronous dynamic random-access memory smos692b july 1997 revised march 1998 3 post office box 1443 ? houston, texas 772511443 operation (continued) table 1. basic command truth table 2 command 3 state of bank(s) cs ras cas w a11 a10 a0 a9 mnemonic mode register set t = deac b = deac l l l l x x a0 a6 = v a8 a7 = 0 a9 = v mrs bank deactivate (precharge) x l l h l bs l x deac deactivate all banks x l l h l x h x dcab bank activate/row-address entry sb = deac l l h h bs v v actv column-address entry / write operation sb = actv l h l l bs l v wrt column-address entry / write operation with auto-deactivate sb = actv l h l l bs h v wrt-p column-address entry/read operation sb = actv l h l h bs l v read column-address entry/read operation with auto-deactivate sb = actv l h l h bs h v read-p burst stop sb = actv l h h l x x x stop no operation x l h h h x x x noop control-input inhibit / no operation x h x x x x x x desl auto refresh t = deac b = deac l l l h x x x refr 2 for execution of these commands on cycle n, one of the following must be true: cke (n1) must be high t cesp must be satisfied for power-down exit t cesp and t rc must be satisfied for self-refresh exit t is and ncle must be satisfied for clock-suspend exit dqmx(n) is a don't care. 3 all other unlisted commands are considered vendor-reserved commands or illegal commands. auto-refresh or self-refresh entry requires that all banks be deactivated or in an idle state prior to the command entry. legend: n = clk cycle number l = logic low h = logic high x = don't care, either logic low or logic high v = valid t = bank t b = bank b actv = activated deac = deactivated bs = logic high to select bank t; logic low to select bank b sb = bank selected by a11 at cycle n
TMS626162A 524288 by 16-bit by 2-bank synchronous dynamic random-access memory smos692b july 1997 revised march 1998 4 post office box 1443 ? houston, texas 772511443 operation (continued) table 2. clock enable (cke) command function table 2 command 3 state of bank(s) cke (n 1) cke (n) cs (n) ras (n) cas (n) w (n) mnemonic self-refresh entry t = deac b = deac h l l l l h slfr power-down entry on cycle (n + 1) t = no access operation ? b = no access operation ? h l x x x x pde self refresh exit t = self refresh l h l h h h e self - refresh e x it b = self refresh l h h x x x e power-down exit # t = power down b = power down l h x x x x e clk suspend on cycle (n + 1) t = access operation ? b = access operation ? h l x x x x hold clk suspend exit on cycle (n + 1) t = access operation ? b = access operation ? l h x x x x e 2 for execution of these commands, a0 a11 (n) and dqmx (n) are don't care entries. 3 all other unlisted commands are considered vendor-reserved commands or illegal commands. on cycle n, the device executes the respective command (listed in table 1). on cycle (n + 1), the device enters power-down mode . ? a bank is no longer in an access operation one cycle after the last data-out cycle of a read operation, and two cycles after th e last data-in cycle of a write operation. neither the pde nor the hold command is allowed on the cycle immediately following the last data-in cycle of a write operation. # if setup time from cke high to the next clk high satisfies t cesp , the device executes the respective command (listed in table 1). otherwise, either desl or noop command must be applied before any other command. legend: n = clk cycle number l = logic low h = logic high x = don't care, either logic low or logic high t = bank t b = bank b deac = deactivated
TMS626162A 524288 by 16-bit by 2-bank synchronous dynamic random-access memory smos692b july 1997 revised march 1998 5 post office box 1443 ? houston, texas 772511443 operation (continued) table 3. data-mask (dqm) command function table 2 command state of bank(s) dqml dqmu 3 (n) data in (n) data out (n + 2) mnemonic e t = deac and b = deac x n/a hi-z e e t = actv and b = actv ( no access operation ) x n/a hi-z e data-in enable t = write or b = write l v n/a enbl data-in mask t = write or b = write h m n/a mask data-out enable t = read or b = read l n/a v enbl data-out mask t = read or b = read h n/a hi-z mask 2 for execution of these commands on cycle n, one of the following must be true: cke (n) must be high t cesp must be satisfied for power-down exit t cesp and t rc must be satisfied for self-refresh exit t is and n cle must be satisfied for clock suspend exit cs (n), ras (n), cas (n), w (n), and a0 a11 are don't cares except for interrupt conditions. 3 dqml controls d 0 d 7 and q 0 q 7. dqmu controls d 8 d 15 and q 8 q15. a bank is no longer in an access operation one cycle after the last data-out cycle of a read operation, and two cycles after th e last data-in cycle of a write operation. neither the pde nor the hold command is allowed on the cycle immediately following the last data-in cycle of a write operation. legend: n = clk cycle number l = logic low h = logic high x = don't care, either logic low or logic high v = valid m = masked input data n/a = not applicable t = bank t b = bank b actv = activated deac = deactivated write = activated and accepting data inputs on cycle n read = activated and delivering data outputs on cycle (n + 2)
TMS626162A 524288 by 16-bit by 2-bank synchronous dynamic random-access memory smos692b july 1997 revised march 1998 6 post office box 1443 ? houston, texas 772511443 burst sequence all data for the '626162a is written or read in a burst fashion, that is, a single starting address is entered into the device and then the '626162a internally accesses a sequence of locations based on that starting address. after the first access, some of the subsequent accesses can be at preceding as well as succeeding column addresses, depending on the starting address entered. this sequence can be programmed to follow either a serial burst or an interleave burst (see table 4 through table 6). the length of the burst can be programmed to be 1, 2, 4, 8, or full-page ( 256 ) accesses (see the section on setting the mode register). after a read burst is complete (as determined by the programmed-burst length), the outputs are in the high-impedance state until the next read access is initiated. table 4. 2-bit burst sequences internal column address a0 decimal binary start 2nd start 2nd serial 0 1 0 1 serial 1 0 1 0 interleave 0 1 0 1 interlea v e 1 0 1 0 table 5. 4-bit burst sequences internal column address a0 a1 decimal binary start 2nd 3rd 4th start 2nd 3rd 4th 0 1 2 3 00 01 10 11 serial 1 2 3 0 01 10 11 00 serial 2 3 0 1 10 11 00 01 3 0 1 2 11 00 01 10 0 1 2 3 00 01 10 11 interleave 1 0 3 2 01 00 11 10 interlea v e 2 3 0 1 10 11 00 01 3 2 1 0 11 10 01 00
TMS626162A 524288 by 16-bit by 2-bank synchronous dynamic random-access memory smos692b july 1997 revised march 1998 7 post office box 1443 ? houston, texas 772511443 burst sequence (continued) table 6. 8-bit burst sequences internal column address a0 a2 decimal binary start 2nd 3rd 4th 5th 6th 7th 8th start 2nd 3rd 4th 5th 6th 7th 8th 0 1 2 3 4 5 6 7 000 001 010 011 100 101 110 111 1 2 3 4 5 6 7 0 001 010 011 100 101 110 111 000 2 3 4 5 6 7 0 1 010 011 100 101 110 111 000 001 serial 3 4 5 6 7 0 1 2 011 100 101 110 111 000 001 010 serial 4 5 6 7 0 1 2 3 100 101 110 111 000 001 010 011 5 6 7 0 1 2 3 4 101 110 111 000 001 010 011 100 6 7 0 1 2 3 4 5 110 111 000 001 010 011 100 101 7 0 1 2 3 4 5 6 111 000 001 010 011 100 101 110 0 1 2 3 4 5 6 7 000 001 010 011 100 101 110 111 1 0 3 2 5 4 7 6 001 000 011 010 101 100 111 110 2 3 0 1 6 7 4 5 010 011 000 001 110 111 100 101 interleave 3 2 1 0 7 6 5 4 011 010 001 000 111 110 101 100 interlea v e 4 5 6 7 0 1 2 3 100 101 110 111 000 001 010 011 5 4 7 6 1 0 3 2 101 100 111 110 001 000 011 010 6 7 4 5 2 3 0 1 110 111 100 101 010 011 000 001 7 6 5 4 3 2 1 0 111 110 101 100 011 010 001 000 latency the beginning data-out cycle of a read burst can be programmed to occur two or three clk cycles after the read command (see the section on setting the mode register). this feature allows adjustment of the device so that it operates using the capability to latch the data output. the delay between the read command and the beginning of the output burst is known as cas latency. after the initial output cycle begins, the data burst occurs at the clk frequency without any intervening gaps. use of minimum read latencies is restricted, based on the maximum frequency rating of the '626162a. there is no latency for data-in cycles (write latency). the first data-in cycle of a write burst is entered at the same rising edge of clk on which the wrt command is entered. the write latency is fixed and is not determined by the mode-register contents. two-bank operation the '626162a contains two independent banks that can be accessed individually or in an interleaved fashion. each bank must be activated with a row address before it can be accessed. each bank must then be deactivated before it can be activated again with a new row address. the bank-activate/row-address-entry command (actv) is entered by holding ras low, cas high, w high, and a11 valid on the rising edge of clk. a bank can be deactivated either automatically during a read-p or a wrt-p command, or by use of the deactivate-bank (deac) command. both banks can be deactivated at once by use of the dcab command (see table 1 and the section on bank deactivation).
TMS626162A 524288 by 16-bit by 2-bank synchronous dynamic random-access memory smos692b july 1997 revised march 1998 8 post office box 1443 ? houston, texas 772511443 two-bank row-access operation the two-bank feature allows access of information on random rows at a higher rate of operation than is possible with a standard dram by activating one bank with a row address and, while the data stream is being accessed to/from that bank, activating the second bank with another row address. when the data stream to or from the first bank is complete, the data stream to or from the second bank can begin without interruption. after the second bank is activated, the first bank can be deactivated to allow the entry of a new row address for the next round of accesses. in this manner, operation can continue in an interleaved fashion. figure 28 is an example of two-bank row-interleaving read bursts with automatic deactivate for a cas latency of three and a burst length of eight. two-bank column-access operation the availability of two banks allows the access of data from random starting columns between banks at a higher rate of operation. after activating each bank with a row address (actv command), a11 can be used to alternate read or wrt commands between the banks to provide gapless accesses at the clk frequency, provided all specified timing requirements are met. figure 29 is an example of two-bank column-interleaving read bursts for a cas latency of three and a burst length of two. bank deactivation (precharge) both banks can be deactivated (placed in precharge) simultaneously by using the dcab command. a single bank can be deactivated by using the deac command. the deac command is entered identically to the dcab command except that a10 must be low and a11 used to select the bank to be precharged as shown in table 1. a bank can be deactivated automatically by using a10 during a read or write command. if a10 is held high during the entry of a read or write command, the accessed bank (selected by a11) is deactivated automatically upon completion of the access burst. if a10 is held low during the entry of a read or write command, that bank remains active following the burst. the read and write commands with automatic deactivation are signified as read-p and wrt-p. chip select (cs ) cs can be used to select or deselect the '626162a for command entry, which might be required for multiple-memory-device decoding. if cs is held high on the rising edge of clk (desl command), the device does not respond to ras , cas , or w until the device is selected again by holding cs low on the rising edge of clk. any other valid command can be entered simultaneously on the same rising clk edge of the select operation. the device can be selected/deselected on a cycle-by-cycle basis (see table 1 and table 2). the use of cs does not affect an access burst that is in progress; the desl command can only restrict ras , cas , and w inputs to the '626162a. data mask the mask command or its opposite, the data-in enable (enbl) command (see table 3), is performed on a cycle-by-cycle basis to gate any data cycle within a read burst or a write burst. dqml controls dq0 dq7, and dqmu controls dq8 dq15. the application of dqmx to a write burst has no latency (n did = 0 cycle), but the application of dqmx to a read burst has a latency of n dod = 2 cycles. during a write burst, if dqmx is held high on the rising edge of clk, the data-input is ignored on that cycle. if dqmx is held high at the rising edge of clk during a read burst, n dod cycles later, the data goes to the high-impedance state. figure 18 and figure 32 through figure 35 show examples of data-mask operations.
TMS626162A 524288 by 16-bit by 2-bank synchronous dynamic random-access memory smos692b july 1997 revised march 1998 9 post office box 1443 ? houston, texas 772511443 clk-suspend/power-down mode for normal device operation, cke should be held high to enable clk. if cke goes low during the execution of a read (read-p) or wrt (wrt-p) operation, the dq bus occurring at the immediate next rising edge of clk is frozen at its current state, and no further inputs are accepted until cke returns high. this is known as a clk-suspend operation, and its execution indicates a hold command. the device resumes operation from the point where it was placed in suspension, beginning with the second rising edge of clk after cke returns high. if cke is brought low when no read or write command is in progress, the device enters power-down mode. if both banks are deactivated when power-down mode is entered, power consumption is reduced to a minimum. power-down mode can be used during row-active or auto-refresh periods to reduce input-buffer power. after power-down mode is entered, no further inputs are accepted until cke returns high. to ensure that data in the device remains valid during the power-down mode, the self-refresh command ( slfr) must be executed concurrently with the power-down entry ( pde) command. when exiting power-down mode, new commands can be entered on the first clk edge after cke returns high, provided that the setup time (t cesp ) is satisfied. table 2 shows the command configuration for a clk-suspend/power-down operation. figure 19, figure 20, and figure 38 show examples of the procedure. setting the mode register the '626162a contains a mode register that must be programmed with the cas latency, the burst type, and the burst length. this is accomplished by executing a mode-register set (mrs) command with the information entered on the address lines a0 a9. a logic 0 must be entered on a7 and a8, but a10 and a11 are don't-care entries for the '626162a. when a9 = 1, the write-burst length is always 1. when a9 = 0, the write-burst length is defined by a0 a2. figure 1 shows the valid combinations for a successful mrs command. only valid addresses allow the mode register to be changed. if the addresses are not valid, the contents of the mode register are undefined, and it will require a valid mrs command for proper operation. the mrs command is executed by holding ras , cas , and w low and the input mode word valid on a0 a9 on the rising edge of clk (see table 1). the mrs command can be executed only when both banks are deactivated. a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 reserved 0 = serial 1 = interleave (burst type) 0 0 register bit a9 write burst lth register bits 2 cas lt 3 register bits 2 burst length bit a9 l engt h a6 a5 a4 l atency 3 a2 a1 a0 burst length 0 1 a0 a2 1 0 0 1 1 0 1 2 3 0 0 0 0 1 0 0 1 1 1 0 1 0 1 1 1 2 4 8 256 2 all other combinations are reserved. 3 see timing requirements for minimum valid read latencies based on maximum frequency rating. figure 1. mode-register programming
TMS626162A 524288 by 16-bit by 2-bank synchronous dynamic random-access memory smos692b july 1997 revised march 1998 10 post office box 1443 ? houston, texas 772511443 refresh the '626162a must be refreshed such that all 4 096 rows are access within t ref (see timing requirements) or data cannot be retained. refresh can be accomplished by performing a series of actv and deac to every row in both banks, 4 096 auto-refresh (refr) commands, or by placing the device in self-refresh mode. regardless of the method used, all rows must be refreshed before t ref has expired. auto refresh (refr) before performing a refr, both banks must be deactivated (placed in precharge). to enter a refr command, ras and cas must be low and w must be high upon the rising edge of clk (see table 1). the refresh address is generated internally such that, after 4 096 refr commands, both banks of the '626162a have been refreshed. the external address and bank select (a11) are ignored. the execution of a refr command automatically deactivates both banks upon completion of the internal auto-refresh cycle, allowing consecutive refr-only commands to be executed, if desired, without any intervening deac commands. the refr commands do not necessarily have to be consecutive, but all 4 096 must be completed before t ref expires. self refresh (slfr) to enter self refresh, both banks of the '626162a must be deactivated and then a self-refresh (slfr) command must be executed (see table 2). the slfr command is identical to the refr command, except that cke is low. for proper entry of the slfr command, cke is brought low for the same rising edge of clk that ras and cas are low and w is high. cke must be held low to stay in self-refresh mode. in the self-refresh mode, all refreshing signals are generated internally for both banks with all external signals (except cke) being ignored. data is retained by the device automatically for an indefinite period when power is maintained, and power consumption is reduced to a minimum. to exit self-refresh mode, cke must be brought high. new commands may only be issued after t rc has expired. if clk is made inactive during self refresh, it must be returned to an active and stable condition before cke is brought high to exit self refresh (see figure 21). if the burst-refresh scheme is used, 4 096 refr commands must be executed prior to entering and upon exiting self-refresh. however, if the distributed-refresh scheme utilizing auto refresh is used (for example, two rows every 32 microseconds), the first set of refreshes must be performed upon exiting self-refresh and before continuing with normal device operation. this ensures that the sdram is fully refreshed. interrupted bursts a read burst or write burst can be interrupted before the burst sequence has been completed with no adverse effects to the operation. this is accomplished by entering certain superseding commands as listed in table 7 and table 8, provided that all timing requirements are met. a deac command is considered an interrupt only if it is issued to the same bank as the preceding read or wrt command. the interruption of read-p or wrt-p operations is not supported.
TMS626162A 524288 by 16-bit by 2-bank synchronous dynamic random-access memory smos692b july 1997 revised march 1998 11 post office box 1443 ? houston, texas 772511443 interrupted bursts (continued) table 7. read-burst interruption interrupting command effect or note on use during read burst read, read-p current output cycles continue until the programmed latency from the superseding-read (read-p) command is met and new output cycles begin (see figure 2). wrt, wrt-p the wrt (wrt-p) command immediately supersedes the read burst in progress. to avoid data contention, dqmx must be held high before the wrt (wrt-p) command to mask output of the read burst on cycles (n ccd -1), n ccd , and (n ccd +1), assuming that there is any output during these cycles (see figure 3). deac, dcab the dq bus is in the high-impedance state when n hzp cycles are satisfied or when the read burst completes, whichever occurs first (see figure 4). stop the dq bus is in the high-impedance state when n bsd cycles are satisfied or when the read burst completes, whichever occurs first. the bank remains active. a new read or write command cannot be entered for at least n bsd after the stop command (see figure 5). clk dq read command at column address c0 c0 c1 c1 + 1 c1 + 2 interrupting read command at column address c1 n ccd = one cycle output burst for the interrupting read command begins here note a: for these examples, assume cas latency = 3 and burst length = 4. figure 2. read burst interrupted by read command clk dq read command interrupting wrt command qd d dqmx n ccd = five cycles see note b notes: a. for this example, assume cas latency = 3 and burst length = 4. b. dqmx must be high to mask output of the read burst on cycles (n ccd 1), n ccd , and (n cdd + 1). figure 3. read burst interrupted by write command
TMS626162A 524288 by 16-bit by 2-bank synchronous dynamic random-access memory smos692b july 1997 revised march 1998 12 post office box 1443 ? houston, texas 772511443 interrupted bursts (continued) dq clk q q n hzp n ccd = two cycles interrupting deac/dcab command read command note a: for this example, assume cas latency = 3 and burst length = 4. figure 4. read burst interrupted by deac command dq clk n ccd = two cycles n bsd read command interrupting stop command new command q q note a: for this example, assume cas latency = 3 and burst length = 4. figure 5. read burst interrupt by stop command table 8. write-burst interruption interrupting command effect or note on use during write burst read, read-p data in on the previous cycle is written; no further data in is accepted (see figure 6). wrt, wrt-p the new wrt (wrt-p) command and data in immediately supersede the write burst in progress (see figure 7). deac, dcab the deac/dcab command immediately supersedes the write burst in progress. dqmx must be used to mask the dq bus so that an interrupt does not violate the write-recovery specification (t wr ) (see figure 8). stop the data on the input pins at the time of the burst-stop command is not written; no further data is accepted. the bank remains active. a new read or write command cannot be entered for at least n bsd cycles after the stop command (see figure 9).
TMS626162A 524288 by 16-bit by 2-bank synchronous dynamic random-access memory smos692b july 1997 revised march 1998 13 post office box 1443 ? houston, texas 772511443 interrupted bursts (continued) clk dq read command dq q n ccd = one cycle wrt command q note a: for these examples, assume cas latency = 3 and burst length = 4. figure 6. write burst interrupted by read command dq clk c1 + 3 c1 + 2 c1 + 1 c1 c0 + 1 c0 n ccd = two cycles wrt command at column address c0 interrupting wrt command at column address c1 note a: for this example, assume burst length = 4. figure 7. write burst interrupted by write command clk dq dd n ccd = two cycles wrt command dqmx t wr ignored interrupting deac or dcab command note a: for this example, assume burst length = 4. figure 8. write burst interrupted by deac/dcab command
TMS626162A 524288 by 16-bit by 2-bank synchronous dynamic random-access memory smos692b july 1997 revised march 1998 14 post office box 1443 ? houston, texas 772511443 interrupted bursts (continued) dq clk ignored ignored d d n bsd n ccd = two cycles interrupting stop command new command wrt command note a: for this example, assume cas latency = 3, burst length = 4. figure 9. write burst interrupted by stop command power up device initialization should be performed after a power up to the full v cc level. after power is established, a 200- m s interval is required (with no inputs other than clk). after this interval, both banks of the device must be deactivated. eight refr commands must be performed, and the mode register must be set to complete the device initialization.
TMS626162A 524288 by 16-bit by 2-bank synchronous dynamic random-access memory smos692b july 1997 revised march 1998 15 post office box 1443 ? houston, texas 772511443 absolute maximum ratings over ambient temperature range (unless otherwise noted) 2 supply voltage range, v cc 0.5 v to 4.6 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . supply voltage range for output drivers, v ccq 0.5 v to 4.6 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . voltage range on any pin (see note 1) 0.5 v to 4.6 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . short-circuit output current 50 ma . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . power dissipation 1 w . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ambient temperature range, t a 0 c to 70 c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . storage temperature range, t stg 55 c to 150 c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 stresses beyond those listed under aabsolute maximum ratingso may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated under arecommended operating conditi onso is not implied. exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. note 1: all voltage values are with respect to v ss . recommended operating conditions min nom max unit v cc supply voltage 3 3.3 3.6 v v ccq supply voltage for output drivers 3 3.3 3.6 v v ss supply voltage 0 v v ssq supply voltage for output drivers 0 v v ih high-level input voltage 2 v cc + 0.3 v v il low-level input voltage (see note 2) 0.3 0.8 v t a ambient temperature 0 70 c note 2: v il min = 1.5 v ac (pulsewidth 5 ns)
TMS626162A 524288 by 16-bit by 2-bank synchronous dynamic random-access memory smos692b july 1997 revised march 1998 16 post office box 1443 houston, texas 772511443 ? electrical characteristics over recommended ranges of supply voltage and ambient temperature (unless otherwise noted) (see note 3) parameter test conditions '626162a-10 unit parameter test conditions min max unit v oh high-level output voltage i oh = 2 ma 2.4 v v ol low-level output voltage i ol = 2 ma 0.4 v i i input current (leakage) 0 v v i v cc + 0.3 v, all other pins = 0 v to v cc 10 m a i o output current (leakage) 0 v v o v cc + 0.3 v, output disabled 10 m a i cc1 o p erating current burst len g th = 1, t rc t rc min cas latency = 2 105 ma i cc1 operating c u rrent g, rc rc i oh /i ol = 0 ma, one bank activated (see note 4) cas latency = 3 115 ma i cc2p precharge standby current in p ower down mode cke v il max, t ck = 15 ns (see note 5) 2 ma i cc2ps precharge standb y c u rrent in po w er - do w n mode cke and clk v il max, t ck = (see note 6) 2 ma i cc2n precharge standby current in non p ower down mode cke v ih min, t ck = 15 ns (see note 5) 25 ma i cc2ns precharge standb y c u rrent in non - po w er - do w n mode cke v ih min, clk v il max, t ck = (see note 6) 2 ma i cc3p active standby current in p ower down mode cke v il max, t ck = 15 ns (see note 5) 3 ma i cc3ps acti v e standb y c u rrent in po w er - do w n mode cke and clk v il max, t ck = (see note 6) 3 ma i cc3n active standby current in non p ower down mode cke v ih min, t ck = 15 ns (see note 5) 30 ma i cc3ns acti v e standb y c u rrent in non - po w er - do w n mode cke v ih min, clk v il max t ck = (see note 6) 15 ma i cc4 burst current pa g e burst, i oh /i ol = 0 ma cas latency = 2 110 ma i cc4 b u rst c u rrent g, oh ol all banks activated, n ccd = one cycle (see note 7) cas latency = 3 140 ma i cc5 auto refresh current t rc t rc min cas latency = 2 85 ma i cc5 a u to - refresh c u rrent t rc t rc min cas latency = 3 95 ma i cc6 self-refresh current cke v il max 2 ma notes: 3. all specifications apply to the device after power-up initialization. all control and address inputs must be stable and valid. 4. control, dq, and address inputs change twice during t rc . 5. control, dq, and address inputs change state once every 30 ns. 6. control, dq, and address inputs do not change (stable). 7. control, dq, and address inputs change state once every cycle.
TMS626162A 524288 by 16-bit by 2-bank synchronous dynamic random-access memory smos692b july 1997 revised march 1998 17 post office box 1443 ? houston, texas 772511443 capacitance over recommended ranges of supply voltage and ambient temperature, f = 1 mhz (see note 8) parameter min max unit c i(s) input capacitance, clk input 4 pf c i(ac) input capacitance, address and control inputs: a0 a11, cs , dqmx, ras , cas , w 5 pf c i(e) input capacitance, cke input 5 pf c o output capacitance 6.5 pf note 8: v cc = 3.3 0.3 v and bias on pins under test is 0 v. ac timing requirements 23 '626162a-10 unit min max unit t ck2 cycle time, clk cas latency = 2 15 ns t ck3 cycle time, clk cas latency = 3 10 ns t ch pulse duration, clk high 3 ns t cl pulse duration, clk low 3 ns t ac2 access time, clk high to data out (see note 9) cas latency = 2 7 ns t ac3 access time, clk high to data out (see note 9) cas latency = 3 7 ns t oh hold time, clk high to data out 3 ns t lz delay time, clk high to dq in low-impedance state (see note 10) 2 ns t hz delay time, clk high to dq in high-impedance state (see note 11) 8 ns t is setup time, address, control, and data input 3 ns t ih hold time, address, control, and data input 1 ns t cesp power-down/self-refresh exit time (see note 12) 10 ns t ras delay time, actv command to deac or dcab command 50 100000 ns t rc delay time, actv, refr, or slfr exit to actv, mrs, refr, or slfr command 80 ns t rcd delay time, actv command to read, read-p, wrt, or wrt-p command (see note 13) 30 ns t rp delay time, deac or dcab command to actv, mrs, refr, or slfr command 30 ns t rrd delay time, actv command in one bank to actv command in the other bank 20 ns t rsa delay time, mrs command to actv, mrs, refr, or slfr command 20 ns t apr final data out of read-p operation to actv, mrs, slfr, or refr command t rp (cl 1) * t ck ns 2 see parameter measurement information for load circuits. 3 all references are made to the rising transition of clk unless otherwise noted. notes: 9. t ac is referenced from the rising transition of clk that precedes the data-out cycle. for example, the first data out t ac is referenced from the rising transition of clk that is cas latency minus one cycle after the read command. access time is measured at output reference level 1.4 v. 10. t lz is measured from the rising transition of clk that is cas latency minus one cycle after the read command. 11. t hz max defines the time at which the outputs are no longer driven and is not referenced to output voltage levels. 12. see figure 20 and figure 21. 13. for read or write operations with automatic deactivate, t rcd must be set to satisfy minimum t ras .
TMS626162A 524288 by 16-bit by 2-bank synchronous dynamic random-access memory smos692b july 1997 revised march 1998 18 post office box 1443 ? houston, texas 772511443 ac timing requirements 23 (continued) '626162a-10 unit min max unit t apw final data in of wrt-p operation to actv, mrs, slfr, or refr command t rp + t clk ns t wr delay time, final data in of wrt operation to deac or dcab command 10 ns t t transition time 1 5 ns t ref refresh interval 64 ms n ccd delay time, read or wrt command to an interrupting command 1 cycle n cdd delay time, cs low or high to input enabled or inhibited 0 0 cycle n cle delay time, cke high or low to clk enabled or disabled 1 1 cycle n cwl delay time, final data in of wrt command to read, read-p, wrt, or wrt-p command 1 cycle n did delay time, enbl or mask command to enabled or masked data in 0 0 cycle n dod delay time, enbl or mask command to enabled or masked data out 2 2 cycle n hzp2 delay time, deac or dcab command to dq in high-impedance state cas latency = 2 2 cycle n hzp3 delay time, deac or dcab command to dq in high-impedance state cas latency = 3 3 cycle n wcd delay time, wrt command to first data in 0 0 cycle n bsd delay time stop command to read or wrt command cas latency = 2 2 cycle n bsd delay time , stop command to read or wrt command cas latency = 3 3 cycle 2 see parameter measurement information for load circuits. 3 all references are made to the rising transition of clk unless otherwise noted.
TMS626162A 524288 by 16-bit by 2-bank synchronous dynamic random-access memory smos692b july 1997 revised march 1998 19 post office box 1443 ? houston, texas 772511443 parameter measurement information the ac timing measurements are based on signal rise and fall times equal to 1 ns (t t = 1 ns) and a midpoint reference level of 1.4 v for lvttl. for signal rise and fall times greater than 1 ns, the reference level should be changed to v ih min and v il max instead of the midpoint level. all specifications referring to read commands are also valid for read-p commands unless otherwise noted. all specifications referring to wrt commands are also valid for wrt-p commands unless otherwise noted. all specifications referring to consecutive commands are specified as consecutive commands for the same bank unless otherwise noted. 1.4 v output under test r l = 50 w c l = 50 pf z o = 50 w figure 10. lvttl-load circuit t ck clk t t t t t ih t t t ih t t t is , t cesp t cl dq, a0 a11, cs , ras , cas , w , dqmx, cke dq, a0 a11, cs , ras , cas , w , dqmx, cke t ch t is figure 11. input-attribute parameters
TMS626162A 524288 by 16-bit by 2-bank synchronous dynamic random-access memory smos692b july 1997 revised march 1998 20 post office box 1443 ? houston, texas 772511443 parameter measurement information clk dq actv command t hz read command t ac t oh t lz cas latency figure 12. output parameters n ccd n cdd t rc t rcd t rp t rrd t rsa read, wrt desl actv actv, refr, self-refresh exit actv deac, dcab actv mrs read, read-p, wrt, wrt-p, deac, dcab command disable deac, dcab actv, mrs, refr, slfr read, read-p, wrt, wrt-p actv, mrs, refr, slfr actv (different bank) actv, mrs, refr, slfr t ras figure 13. command-to-command parameters
TMS626162A 524288 by 16-bit by 2-bank synchronous dynamic random-access memory smos692b july 1997 revised march 1998 21 post office box 1443 ? houston, texas 772511443 parameter measurement information clk dq q qq deac or dcab command n hzp read command t hz note a: for this example, assume cas latency = 3 and burst length = 4. figure 14. read followed by deactivate clk dq q final data out t apr read-p command actv, mrs, refr, or slfr command note a: for this example, assume cas latency = 3 and burst length = 1. figure 15. read with auto-deactivate clk dq d t wr deac or dcab command wrt command wrt command d n cwl note a: for this example, assume burst length = 1. figure 16. write followed by deactivate
TMS626162A 524288 by 16-bit by 2-bank synchronous dynamic random-access memory smos692b july 1997 revised march 1998 22 post office box 1443 ? houston, texas 772511443 parameter measurement information clk dq d t apw actv, mrs, refr, or slfr command wrt command wrt-p command d n cwl t rp figure 17. write with auto-deactivate clk dq d q ignored dqmx wrt command t wr n dod read command enbl command mask command ignored enbl command mask command n dod mask command mask command deac or dcab command note a: for this example, assume cas latency = 3 and burst length = 4. figure 18. dq masking cke dq clk dq dq dq dq n cle t is t ih t ih t is n cle figure 19. clk-suspend operation
TMS626162A 524288 by 16-bit by 2-bank synchronous dynamic random-access memory smos692b july 1997 revised march 1998 23 post office box 1443 ? houston, texas 772511443 parameter measurement information cke clk cke clk t ih t is t cesp t cesp t is t ih clk is don't care, but must be stable before cke high clk is don't care, but must be stable before cke high exit power-down mode if t cesp is satisfied (new command) enter power-down mode last data-out read (read-p) operation last data-in wrt (wrt-p) operation desl or noop command only if t cesp is not satisfied exit power-down mode (new command) enter power-down mode last data-out read (read-p) operation last data-in wrt (wrt-p) operation figure 20. power-down operation
TMS626162A 524288 by 16-bit by 2-bank synchronous dynamic random-access memory smos692b july 1997 revised march 1998 24 post office box 1443 ? houston, texas 772511443 parameter measurement information actv, mrs, or refr command clk cke t cesp t is t ih slfr command clk is don't care, but must be stable before cke high both banks deactivated exit slfr if t cesp is satisfied t rc desl or noop command only until trc is satisfied actv, mrs, or refr command clk cke t cesp t is t ih slfr command clk is don't care, but must be stable before cke high both banks deactivated t rc desl or noop only until trc is satisfied exit slfr noop or desl if t cesp is not satisfied figure 21. self-refresh operation
clk actv t read t deac t abcd r0 r0 c0 parameter measurement information dq dqmx ras cas w a10 a11 a0 a9 cs cke TMS626162A 524 288 by 16-bit by 2-bank synchronous dynamic random-access memory smos692b july 1997 revised march 1998 post office box 1443 houston, texas 772511443 ? 25 burst type bank row burst cycle 2 (d/q) (b/ t ) addr a bcd q t r0 c0 c0 + 1 c0 + 2 c0 + 3 2 column-address sequence depends on programmed burst type and starting column address c0 (see table 5). note a: this example illustrates minimum t rcd for the '626162a-10 at 100 mhz. figure 22. read burst (cas latency = 3, burst length = 4)
actv t wrt t deac t a bcd r0 r0 c0 efgh parameter measurement information clk dq dqmx ras cas w a10 a11 a0 a9 cs cke TMS626162A 524288 by 16-bit by 2-bank synchronous dynamic random-access memory smos692b july 1997 revised march 1998 26 post office box 1443 houston, texas 772511443 ? burst type bank row burst cycle 2 (d/q) (b/ t ) addr a bcde f gh d t r0 c0 c0 + 1 c0 + 2 c0 + 3 c0 + 4 c0 + 5 c0 + 6 c0 + 7 2 column-address sequence depends on programmed burst type and starting column address c0 (see table 6). note a: this example illustrates minimum t rcd for the '626162a-10 at 100 mhz. figure 23. write burst (burst length = 8)
cke actv b wrt b deac b ab r0 r0 c0 cd read b c1 parameter measurement information clk dq dqmx ras cas w a10 a11 a0 a9 cs 3 TMS626162A 524 288 by 16-bit by 2-bank synchronous dynamic random-access memory smos692b july 1997 revised march 1998 post office box 1443 houston, texas 772511443 ? 27 burst type bank row burst cycle 2 (d/q) (b/ t ) addr a bcd d q b b r0 r0 c0 c0 + 1 c1 c1 + 1 2 column-address sequence depends on programmed burst type and starting column address c0 and c1 (see table 4). note a: this example illustrates minimum t rcd for the '626162a-10 at 100 mhz. figure 24. write-read burst (cas latency = 3, burst length = 2)
clk dq dqmx ras cas w a10 a11 a0 a9 cs cke actv t read t wrt-p t abcd r0 r0 c0 efgh ijkl mn o p c1 parameter measurement information TMS626162A 524288 by 16-bit by 2-bank synchronous dynamic random-access memory smos692b july 1997 revised march 1998 28 post office box 1443 houston, texas 772511443 ? burst type bank row burst cycle 2 (d/q) (b/ t ) addr a bcde f gh i j k lmnop q d t t r0 r0 c0 c0 + 1 c0 + 2 c0 + 3 c0 + 4 c0 + 5 c0 + 6 c0 + 7 c1 c1 + 1 c1 + 2 c1 + 3 c1 + 4 c1 + 5 c1 + 6 c1 + 7 2 column-address sequence depends on programmed burst type and starting column address c0 and c1 (see table 6). note a: this example illustrates minimum t rcd for the '626162a-10 at 100 mhz. figure 25. read-write burst with automatic deactivate (cas latency = 3, burst length = 8)
parameter measurement information clk dq dqmx ras cas w a10 a11 a0 a9 cs cke actv t read t wrt-p t abcd r0 r0 c0 efgh i c1 TMS626162A 524 288 by 16-bit by 2-bank synchronous dynamic random-access memory smos692b july 1997 revised march 1998 post office box 1443 houston, texas 772511443 ? 29 burst type bank row burst cycle 2 (d/q) (b/ t ) addr a bcde f gh i q d t t r0 r0 c0 c0 + 1 c0 + 2 c0 + 3 c0 + 4 c0 + 5 c0 + 6 c0 + 7 c1 2 column-address sequence depends on programmed burst type and starting column address c0 (see table 6). note a: this example illustrates minimum t rcd for the '626162a-10 at 100 mhz. figure 26. read burst single write with automatic deactivate (cas latency = 3, burst length = 8)
r0 clk dq0 dq15 dqmx ras cas w a10 a11 a0 a9 cs cke actv b read- p b n n+1 n+2 n+3 r0 c0 n+4 n+5 n+6 n+7 n+9 n+10 n+11 n+12 n+13 n+14 n+253 n+8 n+254 n+255 parameter measurement information TMS626162A 524288 by 16-bit by 2-bank synchronous dynamic random-access memory smos692b july 1997 revised march 1998 30 post office box 1443 houston, texas 772511443 ? burst type bank row burst cycle 2 (d/q) (b/ t ) addr a b c d e f g h i j k l m nopq r s.. q b r0 c0 2 c0 + 1 c0 + 2 c0 + 3 c0 + 4 c0 + 5 c0 + 6 c0 + 7 255 2 column-address sequence depends on programmed burst type and starting column address c0. note a: this example illustrates minimum t rcd for the '626162a-10 at 100 mhz. figure 27. read burst full page (cas latency = 3, burst length = 256)
r0 clk dq dqmx ras cas w a10 a11 a0 a9 cs cke actv b read- p b abcd r0 c0 efgh jklm nopq c1 actv t read- p b actv b read- p t actv t i rs r1 r2 r3 r1 c2 r2 r3 parameter measurement information TMS626162A 524 288 by 16-bit by 2-bank synchronous dynamic random-access memory smos692b july 1997 revised march 1998 post office box 1443 houston, texas 772511443 ? 31 burst type bank row burst cycle 2 (d/q) (b/ t ) addr a b c d e f g h i j k l m nopq r s.. q q q b t b r0 r1 r2 c0 c0 + 1 c0 + 2 c0 + 3 c0 + 4 c0 + 5 c0 + 6 c0 + 7 c1 c1 + 1 c1 + 2 c1 + 3 c1 + 4 c1 + 5 c1 + 6 c1 + 7 c2 c2 + 1 c2 + 2 . . 2 column-address sequence depends on programmed burst type and starting column address c0, c1, and c2 (see table 6). note a: this example illustrates minimum t rcd for the '626162a-10 at 100 mhz. figure 28. two-bank row-interleaving read bursts with automatic deactivate (cas latency = 3, burst length = 8)
dq clk actv b actv t read t abcd r0 c0 ef dqmx ras cas w a10 a11 a0 a9 cs cke read b read t read b read b r1 c1 c2 c3 c4 r0 r1 parameter measurement information TMS626162A 524288 by 16-bit by 2-bank synchronous dynamic random-access memory smos692b july 1997 revised march 1998 32 post office box 1443 houston, texas 772511443 ? burst type bank row burst cycle 2 (d/q) (b/ t ) addr a b c d e f ... ... q q q . b t b ... r0 r1 r0 ... c0 c0 + 1 c1 c1 + 1 c2 c2 + 1 ... ... 2 column-address sequence depends on programmed burst type and starting column address c0, c1, and c2 (see table 4). figure 29. two-bank column-interleaving read bursts (cas latency = 3, burst length = 2)
r0 clk actv b read b abcd r0 c0 efgh c1 deac t wrt t deac b actv t dqmx ras cas w a10 a11 a0 a9 cs cke dq parameter measurement information r1 r1 TMS626162A 524 288 by 16-bit by 2-bank synchronous dynamic random-access memory smos692b july 1997 revised march 1998 post office box 1443 houston, texas 772511443 ? 33 burst type bank row burst cycle 2 (d/q) (b/ t ) addr a bcde f gh q d b t r0 r1 c0 c0 + 1 c0 + 2 c0 + 3 c1 c1 + 1 c1 + 2 c1 + 3 2 column-address sequence depends on programmed burst type and starting column address c0 and c1. (refer to table 5.) note a: this example illustrates minimum t rcd for the '626162a-10 at 100 mhz. figure 30. read-burst bank b, write-burst bank t (cas latency = 3, burst length = 4)
dq clk actv b abcd r0 r0 ef dqmx ras cas w a10 a11 a0 a9 cs cke read- p b actv t wrt- p t r1 g r1 c0 c1 parameter measurement information TMS626162A 524288 by 16-bit by 2-bank synchronous dynamic random-access memory smos692b july 1997 revised march 1998 34 post office box 1443 houston, texas 772511443 ? burst type bank row burst cycle 2 (d/q) (b/ t ) addr a bcde f gh d q t b r0 r1 c0 c0 + 1 c0 + 2 c0 + 3 c1 c1 + 1 c1 + 2 c1 + 3 2 column-address sequence depends on programmed burst type and starting column address c0 and c1 (see table 5). note a: this example illustrates minimum n cwl for the '626162a-10 at 100 mhz. figure 31. write-burst bank t, read-burst bank b with automatic deactivate (cas latency = 3, burst length = 4)
TMS626162A 524 288 by 16-bit by 2-bank synchronous dynamic random-access memory smos692b july 1997 revised march 1998 post office box 1443 houston, texas 772511443 ? 35 burst type bank row burst cycle 2 (d/q) (b/ t ) addr a bcde f gh q d t t r0 r1 c0 c0 + 1 c0 + 2 c0 + 3 c1 c1 + 1 c1 + 2 c1 + 3 2 column-address sequence depends on programmed burst type and starting column address c0 and c1 (see table 5). note a: this example illustrates minimum t rcd for the '626162a-10 at 100 mhz. figure 32. data mask (cas latency = 3, burst length = 4) dq r0 clk actv t read t ac d r0 c0 f h c1 dcab wrt t dqmx ras cas w a10 a11 a0 a9 cs cke parameter measurement information
parameter measurement information dq0 dq7 clk actv b actv t read t abcd r0 c0 ef dqmu ras cas w a10 a11 a0 a9 cs cke read b read t read b read b r1 c1 c2 c3 c4 r0 r1 dqml hi z dq8 dq15 TMS626162A 524288 by 16-bit by 2-bank synchronous dynamic random-access memory smos692b july 1997 revised march 1998 36 post office box 1443 houston, texas 772511443 ? burst type bank row burst cycle 2 (d/q) (b/ t ) addr a bcde f gh q q q q t b t b r0 r1 r0 r1 c0 c0 + 1 c1 c1+1 c2 c1+1 c3 c3+ 1 2 column-address sequence depends on programmed burst type and starting column address c0, c1, and c2 (see table 4). figure 33. data mask with byte control (cas latency = 3, burst length = 2)
parameter measurement information r1 r0 clk actv b read b r0 c0 c1 deac t wrt t deac b actv t r1 dqmu ras cas w a10 a11 a0 a9 cs cke dq0 dq7 abcd efgh dqml dq8 dq15 TMS626162A 524 288 by 16-bit by 2-bank synchronous dynamic random-access memory smos692b july 1997 revised march 1998 post office box 1443 houston, texas 772511443 ? 37 burst type bank row burst cycle 2 (d/q) (b/ t ) addr a bcde f gh q d t b r0 r1 c0 c0 + 1 c0 + 2 c0 + 3 c1 c1 + 1 c1 + 2 c1 + 3 2 column-address sequence depends on programmed burst type and starting column address c0 and c1 (see table 5). note a: this example illustrates minimum t rcd read burst for the '626162a-10 at 100 mhz. figure 34. data mask with byte control (cas latency = 3, burst length = 4)
parameter measurement information dq0 dq7 r0 clk actv t read t a b cd r0 c0 fh c1 dcab wrt b actv b r1 dqml ras cas w a10 a11 a0 a9 cs cke dq8 dq15 acd fh dqmu b e g r1 TMS626162A 524288 by 16-bit by 2-bank synchronous dynamic random-access memory smos692b july 1997 revised march 1998 38 post office box 1443 houston, texas 772511443 ? burst type bank row burst cycle 2 (d/q) (b/ t ) addr a bcde f gh q d t b r0 r1 c0 c0 + 1 c0 + 2 c0 + 3 c1 c1 + 1 c1 + 2 c1 + 3 2 column-address sequence depends on programmed burst type and starting column address c0 and c1 (see table 5). note a: this example illustrates minimum t rcd for the '626162a-10 at 100 mhz. figure 35. data mask with cycle-by-cycle byte control (cas latency = 3, burst length = 4)
clk dq dqmx ras cas w a10 a11 a0 a9 cs cke refr deac t a r0 bcd r0 actv t read t refr c0 parameter measurement information TMS626162A 524 288 by 16-bit by 2-bank synchronous dynamic random-access memory smos692b july 1997 revised march 1998 post office box 1443 houston, texas 772511443 ? 39 burst type bank row burst cycle 2 (d/q) (b/ t ) addr a bcd q t r0 c0 c0 + 1 c0 + 2 c0 + 3 2 column-address sequence depends on programmed burst type and starting column address c0 (see table 5). note a: this example illustrates minimum t rc and t rcd for the '626162a-10 at 100 mhz. figure 36. refresh cycles (cas latency = 3, burst length = 4)
abcd see note b clk dcab dq dqmx ras cas w a10 a11 a0 a9 cs cke mrs wrt-p b actv b r0 see note b see note b parameter measurement information c0 r0 TMS626162A 524288 by 16-bit by 2-bank synchronous dynamic random-access memory smos692b july 1997 revised march 1998 40 post office box 1443 houston, texas 772511443 ? burst type bank row burst cycle 2 (d/q) (b/ t ) addr a bcd d b r0 c0 c0 + 1 c0 + 2 c0 + 3 2 column-address sequence depends on programmed burst type and starting column address c0 (see table 5). notes: a. this example illustrates minimum t rp , t rsa , and t rcd for the '626162a-10 at 100 mhz. b. see figure 1. figure 37. set mode register (deactivate all, set mode register, write burst with automatic deactivate) (cas latency = 2, burst length = 4)
b c0 clk dq0 dqmx ras cas w a10 a11 a0 a9 cs cke actv t read t a c d r0 gh c1 hold wrt-p t r0 parameter measurement information f hold e pde TMS626162A 524 288 by 16-bit by 2-bank synchronous dynamic random-access memory smos692b july 1997 revised march 1998 post office box 1443 houston, texas 772511443 ? 41 burst- type bank row burst cycle 2 (d/q) (b/ t ) addr a bcde f gh q d t t r0 r1 c0 c0 + 1 c0 + 2 c0 + 3 c1 c1 + 1 c1 + 2 c1 + 3 2 column-address sequence depends on programmed burst type and starting column address c0 and c1 (see table 5). figure 38. clk suspend (hold) during read burst and write burst (cas latency = 3, burst length = 4)
TMS626162A 524288 by 16-bit by 2-bank synchronous dynamic random-access memory smos692b july 1997 revised march 1998 42 post office box 1443 ? houston, texas 772511443 device symbolization speed code (-10, -12) package code lot traceability code month code year code die revision code wafer fab code -ss llll m y b w TMS626162A dge ti assembly site code p
TMS626162A 524288 by 16-bit by 2-bank synchronous dynamic random-access memory smos692b july 1997 revised march 1998 43 post office box 1443 ? houston, texas 772511443 mechanical data dge (r-pdso-g50) plastic small-outline package 4040070-5 / c 12/95 gage plane 0.404 (10,26) 0.396 (10,06) 0.471 (11,96) 0.455 (11,56) 0.006 (0,15) nom 0.024 (0,60) 0.016 (0,40) seating plane 0.010 (0,25) 0.821 (20,85) 0.829 (21,05) 50 1 0.047 (1,20) max 0.000 (0,00) min 0.018 (0,45) 26 0.012 (0,30) 25 0.004 (0,10) m 0.006 (0,16) 0.031 (0,80) 0 5 notes: a. all linear dimensions are in inches (millimeters). b. this drawing is subject to change without notice. c. body dimensions do not include mold flash or protrusion.
important notice texas instruments (ti) reserves the right to make changes to its products or to discontinue any semiconductor product or service without notice, and advises its customers to obtain the latest version of relevant information to verify, before placing orders, that the information being relied on is current and complete. ti warrants performance of its semiconductor products and related software to the specifications applicable at the time of sale in accordance with ti's standard warranty. testing and other quality control techniques are utilized to the extent ti deems necessary to support this warranty. specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. certain applications using semiconductor products may involve potential risks of death, personal injury, or severe property or environmental damage (acritical applicationso). ti semiconductor products are not designed, intended, authorized, or warranted to be suitable for use in life-support applications, devices or systems or other critical applications. inclusion of ti products in such applications is understood to be fully at the risk of the customer. use of ti products in such applications requires the written approval of an appropriate ti officer. questions concerning potential risk applications should be directed to ti through a local sc sales office. in order to minimize risks associated with the customer's applications, adequate design and operating safeguards should be provided by the customer to minimize inherent or procedural hazards. ti assumes no liability for applications assistance, customer product design, software performance, or infringement of patents or services described herein. nor does ti warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of ti covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. copyright ? 1998, texas instruments incorporated

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